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CoreU1PHY – UTOPIA Level 1 PHY Interface
Device Requirements
CoreU1PHY can be implemented in either the ProASIC PLUS or Axcelerator device families. Table 1 indicates the number
of core logic cells required in each technology.
Table 1 ? Device Utilization and Performance
Cells or Tiles
Total Utilization
ProASIC
Family
Fusion
ProASIC3/E
PLUS
Axcelerator
Sequential
59
59
79
60
Combinatorial
61
61
58
60
Device
AFS060
A3P060
APA075
AX125
Percentage
8.0%
8.0%
4.5%
6.0%
Performance
25 MHz
25 MHz
>25 MHz
>25 MHz
UTOPIA Interface
CoreU1PHY implements a standard 8-bit point-to-point
physical-layer interface that supports cell lengths of
either 53 or 54 bytes. If the cell_size bit is low, a 53-byte
cell is transferred and the UDF2 byte is inserted on
ingress to and dropped on egress from the user
interface; otherwise, 54 bytes are transferred. The
UTOPIA interface signals are summarized in Table 2 .
Table 2 ? UTOPIA Interface Signals
CoreU1PHY will then look for u1_tx_soc to become
active (high), indicating that the first word of the cell
transfer is active on the bus. As shown in Figure 2 ,
u1_tx_soc may be asserted during the same cycle that
u1_tx_en is driven low. Once u1_tx_soc is recognized, the
core accepts 53 bytes (or 54) and forwards them to the
user interface.
Signal
Type Description
u1_tx_clk
u1_tx_clk
u1_tx_clav
u1_tx_en
In
Out
In
TX interface clock
Active high cell buffer space available
Active low data transfer enable
u1_tx_clav
u1_tx_en
u1_tx_soc
u1_tx_soc
In
Active high start-of-cell indication
u1_tx_data
H1
H2
u1_tx_data
u1_rx_clk
u1_rx_clav
u1_rx_en
u1_rx_soc
u1_rx_data
In
In
Out
In
Out
Out
8-bit ingress data
RX interface clock
Active high cell buffer space available
Active low data transfer enable
Active high start-of-cell indication
8-bit ingress data
Figure 2 ? TX Start of Cell
If the link-layer device does not have another cell to
send, or if polling during the current cell transfer
indicates that the CoreU1PHY is not ready to accept
another cell, the U1 link-layer may deselect the physical
interface by de-asserting u1_tx_en after the last word of
the transfer ( Figure 3 ).
TX Interface (Ingress)
The process of transferring a cell on the UTOPIA level 1
TX interface begins with u1_tx_clav. The core asserts
u1_tx_clav high whenever w_avail is asserted at the user
interface. If u1_tx_clav is low, the link-layer device must
u1_tx_clk
u1_tx_clav
u1_tx_en
u1_tx_soc
wait until CoreU1PHY indicates that it is ready to receive
another cell.
u1_tx_data
P51 P52 P53 P54
XX
To begin sending cells on the TX interface, the link-layer
simply asserts u1_tx_en low ( Figure 2 ).
Figure 3 ? TX Transfer Complete
2
v4.0
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相关代理商/技术参数
COREU1PHY-EV 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1PHY - UTOPIA Level 1 PHY Interface
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